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Integrated Circuit Systems, Inc.
ICS9158-03
Frequency Generator and Integrated Buffer
General Description
The ICS9158-03 is a low-cost frequency generator designed specifically for desktop and notebook PC applications. Eight copies of the CPU clock are available. Each high drive (40mA) output is capable for driving a 30pF load and has a typical duty cycle of 50/50. The clock outputs are skew-controlled to within 250ps. The ICS9158-03 makes a gradual transition between frequencies, so that it meets the Intel cycle-to-cycle timing specification for 486 and Pentium systems.
Features
8 skew-free, high drive CPU/BUS clocks Up to 100 MHz output 250ps skew between all outputs Outputs can drive up to 30pF load and 40mA 5010% duty cycle Compatible with 486 and Pentium CPUs On-chip loop filter components 4.5V - 5.5V supply range 24-pin SOIC package
Applications
Ideal for RISC or CISC systems such as 486, Pentium, PowerPC, etc. requiring multiple CPU and BUS clocks.
Block Diagram
9158-03 Rev D 7/28/98
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9158-03
Pin Configuration
24-Pin SOIC
Functionality
(Assuming 14.318 MHz input.) VDD=5V10% or 3.3V10%, TEMP=0-70C
FS2 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
CLK2A (MHz) 32 32 32 32 50 50 66.67 60
CLK12(A-C) (MHZ) 16 32 16 32 25 50 33.33 60
CLK1(A-D) (MHz) 16 16 16 16 25 25 33.33 30
Peripheral Clocks
OE 1 0 CLK2A Runs Tristate CLK12(A-C) Runs Tristate CLK12(A-D) Runs Tristate 40MHz (Pin 6) 39.92 Tristate 24MHz (Pin 7) 23.95 Tristate REF (Pin 18) 14.31818 Tristate
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ICS9158-03
Pin Descriptions for ICS9158-03
PIN NUM BER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAM E CLK1A X2 X1 VDD GND 40 M Hz 24 M Hz CLK1B AGND OE CLK12B GND CLK1C CLK1D FS2 AVDD CLK12A REF GND VDD CLK12C CLK2A FS1 FS0 TYPE OUT OUT IN PW R PW R OUT OUT OUT PW R IN OUT PW R OUT OUT IN PW R OUT OUT PW R PW R OUT OUT IN IN CLK1A clock output Crystal connection Crystal connection Digital POW ER SUPPLY (+5V) Digital GROUND 40 M Hz clock output 24 M Hz floppy disk/com bination I/O clock output CLK1B clock output ANALOG GROUND OUTPUT ENABLE. Tristates all outputs when low. CLK12B clock output Digital GROUND CLK1C clock output CLK1D clock output CPU clock frequency select 2 ANALOG power supply (+5V) CLK12A clock output 14.31818 M Hz clock output Digital GROUND Digital POW ER SUPPLY (+5V) 2X CPU clock output CPU clock output CPU clock frequency select 1 CPU clock frequency select 0 DESCRIPTION
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ICS9158-03
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +150C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 5V
VDD = +5V10%, TA=0C to 70C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage1 Output Low Current1 Output High Current1 Supply Current Output Frequency Change over Supply and Temperature1 Short circuit current1 Pull-up resistor value1 Input Capacitance
1
SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IDD FD ISC RPU Ci CL
TEST CONDITIONS
MIN 2.0
TYP
MAX 0.8
UNITS V V A
VIN=0V (Pull-up) VIN=VDD IOL=20.0mA IOH=-30mA VOL=0.8V VOH=2.0V No load, 66 MHz With respect to typical frequency Each output clock Input pin Except X1, X2 Pins X1, X2
-20 -5 0.25 2.4 45 3.5 65 -55 67 0.002 25 56 680 8 20 -35 100 0.01 5 0.4
A V V mA mA mA % mA k pf pf
Load Capacitance1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9158-03
Electrical Characteristics (continued)
VDD = +5V10%, TA=0C to 70C unless otherwise stated
AC Characteristics PARAMETER Output Rise time, 0.8 to 2.0V (Note 1) Rise time, 20% to 80% VDD (Note 1) Output Fall time, 2.0 to 0.8V1 Fall time, 80% to 20% VDD1 Duty cycle1 Jitter, one sigma1 Jitter, absolute Jitter, absolute Input Frequency Clock skew between CLK2A, CLK1(A-D) and CLK12(A-C) outputs Frequency Transition Time1 SYMBOL tr tr tf tf dt tj1s tjab tjab fi Tsk tft From 4 to 50 MHz -250 TEST CONDITIONS 30pf load 30pf load 30pf load 30pf load 30pf load As compared with clock period 25-66MHz clocks MIN 45/55 TYP 1 2.5 0.5 1.5 48/52 0.5 -5 -250 14.318 100 13 250 20 2 MAX 2.0 3 2.0 3.0 55/45 2.0 5 250 UNITS ns ns ns ns % % % ps MHz ps ms
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9158-03
Electrical Characteristics at 3.3V
VDD = +3.3V10%, TA=0C to 70C unless otherwise stated
PARAM ETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage 1 Output Low Current1 Output High Current 1 Supply Current Output Frequency Change over Supply and Temperature 1 Short Circuit Current1 Pull-up Resistor Value 1 Input Capacitance 1 Load Capacitance 1 SYM BOL VIL VIH IIL IIH VOL VOH IOL IOH IDD FD ISC RPU Ci CL DC Characteristics TEST CONDITIONS M IN 0.7 VDD -10 -5 0.1VDD 0.85VDD 20 30 -15 43 0.002 25 56 900 8 20 TYP M AX 0.2 VDD UNITS V V A A V V mA mA mA % mA kW pF pF
V IN= 0V(Pull-up) V IN= VDD IOL=10mA IOH=-5mA V OL=0.2V DD V OH= 0.7VDD No load, 66 M Hz With respect to typical frequency Each output clock Input pin Except X1, X2 Pins X1, X2
AC C h aracteristics
-10 70 0.01
PA R A M E T E R O utput R ise tim e, 0.8 to 2.0V 1 R ise tim e, 20% to 80% V D D 1 O utput Fall tim e, 2.0 to 0.8V 1 Fall tim e, 80% to 20% V D D 1 D uty cycle 1 Jitter, one sigm a 1 Jitter, absolute 1 Jitter, absolute 1 Input Frequency C lock skew w indow betw een C L K 2A , C L K 1(A -D ) C PU and C L K 12(A -C ) outputs 1 F requency Transition tim e 1
SY M B O L tr tr tf tf dt tj1s tjab tjab fi T sk tft
T E ST C O N D IT IO N S 30pF load 30pF 30pF 30pF 30pF load load load load
M IN 40/50
TYP 1 2.5 0.5 1.5 44/46 0.5 2 14.318 100
M AX 2.5 4.0 2.5 4.0 50/40 2.0 5 300
U N IT S ns ns ns ns % % % ps MHz ps ms
A s com pared w ith clock period 25-66 M H z clocks
250 20
From 4 to 50 M H z
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Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9158-03
LEAD COUNT DIMENSION L
24L 0.604
24 Lead SOIC Ordering Information
ICS9158-03CW24
Example:
ICS XXXX-PPP W
Package Type
W=(SOIC) 300mil
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device
7
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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